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Microchip Technology /ATSAMD51J18A /SUPC /VREG

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Interpret as VREG

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ENABLE)ENABLE 0 (LDO)SEL 0 (RUNBKUP)RUNBKUP 0 (VSEN)VSEN 0VSPER

SEL=LDO

Description

VREG Control

Fields

ENABLE

Enable
SEL

Voltage Regulator Selection

0 (LDO): LDO selection

1 (BUCK): Buck selection
RUNBKUP

Run in Backup mode
VSEN

Voltage Scaling Enable
VSPER

Voltage Scaling Period

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data